ARM Cortex-M3 User Manual

Bus Interface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 12-15
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12.12 Memory attributes
The processor exports memory attributes on the System bus by the addition of a
sideband bus, MEMATTR.
Table 12-3 shows the relationship between MEMATTR[0] and HPROT[3:2].
Table 12-3 Memory attributes
MEMATTR[0] HPROT[3] HPROT[2] Description
0 0 0 Strongly ordered
0 01Device
0 1 0 L1 cacheable, L2 not cacheable
1 00Invalid
1 01Invalid
1 1 0 Cache WT, allocate on read
0 1 1 Cache WB, allocate on read and write
1 1 1 Cache WB, allocate on read

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit