ARM Cortex-M3 User Manual

Signal Descriptions
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A.12 ETM interface
Table A-12 lists the signals of the ETM interface.
Table A-12 ETM interface
Name Direction Description
ETMTRIGGER[3:0] Output Trigger from DWT. One bit for each of the four DWT comparators.
ETMTRIGINOTD[3:0] Output Indicates if the ETM is triggered on an instruction or data match.
ETMIVALID Output Instruction valid.
ETMIA[31:1] Output PC of the instruction being executed.
ETMICCFAIL Output Condition Code fail. Indicates if the current instruction has failed or passed its
conditional execution check.
ETMIBRANCH Output Opcode is a branch target.
ETMIINDBR Output Opcode is an indirect branch target.
ETMINTSTAT[2:0] Output Interrupt status. Marks interrupt status of current cycle.
000 - no status
001 - interrupt entry
010 - interrupt exit
011 - interrupt return
100 - vector fetch and stack push.
ETMINTSTAT entry/return is asserted in the first cycle of the new interrupt
context. Exit occurs without ETMIVALID.
ETMINTNUM[8:0] Output Marks the interrupt number of the current execution context.
ETMISTALL Output Indicates that the last instruction signalled by the core has not yet entered
execute.
ETMFLUSH Output A PC modifying opcode has executed, or an interrupt push/pop has started.
ETMPWRUP Input ETM is enabled
ETMDVALID Output Data valid
ETMCANCEL Output Instruction cancelled
ETMFINDBR Output Flush is indirect. Marks flush hint destination cannot be inferred from the PC.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit