ARM Cortex-M3 User Manual

Embedded Trace Macrocell
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14.6 ETM programmer’s model
The ETM programmer’s model is described in detail in the ARM Embedded Trace
Macrocell Architecture Specification. This section defines the implementation-specific
features of the ETM programmer’s model.
14.6.1 Advanced Peripheral Bus interface
The ETM contains an APB slave interface that can read and write to the ETM registers.
This interface is synchronous to the processor clock. The core and the external debug
interface can access it through the Serial Wire Debug Port/JTAG Debug Port
(SW-DP/JTAG-DP).
14.6.2 List of ETM registers
The ETM registers are listed in Table 14-9. For full details, see the ARM Embedded
Trace Macrocell Architecture Specification.
Table 14-9 ETM registers
Name Type Address Present Description
ETM Control Read/write
0xE0041000 Yes For a description, see page 14-19.
Configuration Code Read only
0xE0041004 Yes For a description, see page 14-20.
Trigger Event Read/write
0xE0041008 Yes Defines the event that controls the
trigger.
[16:14] Boolean function.
[13:7] Resource A.
[6:0] Resource B
See ETM Event resources on
page 14-22.
ASIC Control -
0xE004100C No -
ETM Status Read/write
0xE0041010 Yes Provides information on the
current status of the trace and
trigger logic.
[3] - Trigger Flag.
[2] - Start/Stop resource status.
[1] - Programming bit status.
[0] - Untraced Overflow.
System Configuration Read only
0xE0041014 Yes For a description, see page
page 14-20.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit