To Next Page

To Previous Page

Memory Map

Non-Confidential

Unrestricted Access

Table 4-2 shows the permissions of the processor memory regions.

Note

Private Peripheral Bus and System space at

0xE0000000 - 0xFFFFFFFF

are permanently

XN. The MPU cannot change this.

For a description of the processor bus interfaces, see Chapter 12 Bus Interface.

Table 4-2 Memory region permissions

Name Region Device type XN Cache

Code

0x00000000-0x1FFFFFFF

Normal - WT

SRAM

0x20000000-0x3FFFFFFF

Normal - WBWA

SRAM_1M +0000000 - - -

SRAM_31M +0100000 - -

SRAM_bitband +2000000 Internal - -

SRAM +4000000 - - -

Peripheral

0x40000000-0x5FFFFFFF

Device XN -

Periph_1IM +0000000 - - -

Periph_31IM +0100000 - - -

Periph_bit band +2000000 Internal - -

Peripheral +4000000 - - -

External RAM

0x60000000-0x7FFFFFFF

Normal - WBWA

External RAM

0x80000000-0x9FFFFFFF

Normal - WT

External Device

0xA0000000-0xBFFFFFFF

Device XN -

External Device

0xC0000000-0xDFFFFFFF

Device XN -

System

0xE0000000-0xFFFFFFFF

-XN-

Private Peripheral Bus +0000000 SO, shared XN -

Vendor_SYS +0100000 Device XN -

Questions and Answers:

Need help?

Do you have a question about the ARM Cortex-M3 and is the answer not in the manual?

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit