ARM Cortex-M3 User Manual

Preface
xx Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
About this book
This book is for the Cortex-M3 processor.
Product revision status
The rnpn identifier indicates the revision status of the product described in this manual,
where:
rn Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
This manual is written to help system designers, system integrators, and verification
engineers who are implementing a System-on-Chip (SoC) device based on the
Cortex-M3 processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for a description of the components of the processor, and about
the processor instruction set.
Chapter 2 Programmer’s Model
Read this for a description of the processor register set, modes of
operation, and other information for programming the processor.
Chapter 3 System Control
Read this for a description of the registers and programmer’s model for
system control.
Chapter 4 Memory Map
Read this for a description of the processor memory map and bit-banding
feature.
Chapter 5 Exceptions
Read this for a description of the processor exception model.
Chapter 6 Clocking and Resets
Read this chapter for a description of the processor clocking and resets.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit