ARM Cortex-M3 User Manual

Preface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. xxi
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Chapter 7 Power Management
Read this for a description of the processor power management and
power saving.
Chapter 8 Nested Vectored Interrupt Controller
Read this for a description of the processor interrupt processing and
control.
Chapter 9 Memory Protection Unit
Read this for a description of the processor Memory Protection Unit
(MPU).
Chapter 10 Core Debug
Read this chapter to learn about debugging and testing the processor core.
Chapter 11 System Debug
Read this for a description of the processor system debug components.
Chapter 13 Debug Port
Read this for a description of the processor debug port, and the Serial
Wire JTAG Debug Port (SWJ-DP) and Serial Wire Debug Port (SW-DP).
Chapter 17 Trace Port Interface Unit
Read this chapter to learn about the processor Trace Port Interface Unit
(TPIU).
Chapter 12 Bus Interface
Read this for a description of the processor bus interfaces.
Chapter 14 Embedded Trace Macrocell
Read this for a description of the processor Embedded Trace Macrocell
(ETM).
Chapter 15 Embedded Trace Macrocell Interface
Read this for a description of the processor ETM interface.
Chapter 16 AHB Trace Macrocell Interface
Read this for a description of the processor Advanced High-performance
Bus (AHB) trace macrocell interface.
Chapter 18 Instruction Timing
Read this for a description of the processor instruction timing and clock
cycles.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit