ARM Cortex-M3 User Manual

Instruction Timing
18-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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18.1 About instruction timing
The timing information in this chapter covers each instruction in addition to interactions
between instructions. It also contains information about factors that influence timings.
When looking at timings, it is important to understand the role that the system
architecture plays. Every instruction must be fetched and every load/store must go out
to the system. These factors are described along with intended system design, and the
implications for timing.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit