ARM Cortex-M3 User Manual

Bus Interface
12-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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12.1 About bus interfaces
The processor contains four bus interfaces:
• The ICode memory interface. Instruction fetches from Code memory space
(
0x0000000 - 0x1FFFFFFF) are performed over this 32-bit Advanced
High-performance Bus (AHB)-Lite bus. For more information, see ICode bus
interface on page 12-4.
• The DCode memory interface. Data and debug accesses to Code memory space
(
0x0000000 - 0x1FFFFFFF ) are performed over this 32-bit AHB-Lite bus. For more
information, see DCode bus interface on page 12-6.
• The System interface. Instruction fetches, and data and debug accesses, to System
space (
0x20000000 - 0xDFFFFFFF , 0xE0100000 - 0xFFFFFFFF ) are performed over
this 32-bit AHB-Lite bus. For more information, see System interface on
page 12-7.
•The External Private Peripheral Bus (PPB). Data and debug accesses to External
PPB space (
0xE0040000 - 0xE00FFFFF ) are performed over this 32-bit Advanced
Peripheral Bus (APB) (AMBA v3.0) bus. The Trace Port Interface Unit (TPIU)
and vendor specific peripherals are on this bus. For more information, see
External private peripheral interface on page 12-10.
Note
The processor contains an internal PPB for accesses to the Nested Vectored Interrupt
Controller (NVIC), Data Watchpoint and Trace (DWT), Instrumentation Trace
Macrocell (ITM), Flash Patch and Breakpoint (FPB), and Memory Protection Unit
(MPU).

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit