ARM Cortex-M3 User Manual

ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 12-1
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Chapter 12
Bus Interface
This chapter describes the processor bus interface. It contains the following sections:
• About bus interfaces on page 12-2
• AMBA 3 compliance on page 12-3
• ICode bus interface on page 12-4
• DCode bus interface on page 12-6
• System interface on page 12-7
• Unifying the code buses on page 12-9
• External private peripheral interface on page 12-10
• Access alignment on page 12-11
• Unaligned accesses that cross regions on page 12-12
• Bit-band accesses on page 12-13
• Write buffer on page 12-14
• Memory attributes on page 12-15
• AHB timing characteristics on page 12-16.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit