ARM Cortex-M3 User Manual

Memory Protection Unit
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 9-9
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Figure 9-5 MPU Region Attribute and Size Register bit assignments
Table 9-6 describes the bit assignments of the MPU Region Attribute and Size Register.
For more information, see MPU access permissions on page 9-13.
31 29 28 27 26 24 23 22 21 19 18 17 16 15 8 7 6 5 1 0
Res
SRD SIZE
X
N
e
s
R
AP Res. TEX S C B Res.
E
N
A
Table 9-6 MPU Region Attribute and Size Register bit assignments
Bits Field Function
[31:29] - Reserved.
[28] XN Instruction access disable bit:
1 = disable instruction fetches
0 = enable instruction fetches.
[27] - Reserved.
[26:24] AP Data access permission field:
Value Privileged permissions User
permissions
b000
b001
b010
b011
b100
b101
b110
b111
No access
Read/write
Read/write
Read/write
Reserved
Read-only
Read-only
Read-only
No access
No access
Read-only
Read/write
Reserved
No access
Read-only
Read-only.
[23:22] - Reserved.
[21:19] TEX Type extension field.
[18] S Shareable bit:
1 = shareable
0 = not shareable.
[17] C Cacheable bit:
1 = cacheable
0 = not cacheable.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit