ARM Cortex-M3 User Manual

Instruction Timing
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 18-3
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18.2 Processor instruction timings
Table 18-1 shows the Thumb subset supported in the ARMv7-M architecture. It
provides cycle information including annotations to explain how instruction stream
interactions affect timing. System effects, such as running code from slower memory,
are also considered.
Table 18-1 Instruction timings
Instruction type Size Cycles count Description
Data operations 16
1 (+P
a
if PC is destination)
ADC, ADD, AND, ASR, BIC, CMN, CMP, CPY, EOR,
LSL, LSR, MOV, MUL, MVN, NEG, ORR, ROR, SBC,
SUB, TST, REV, REV16, REVSH, SXTB, SXTH, UXTB,
and UXTH. MUL is one cycle.
Branches 16
1+P
a
B<cond>, B, BL, BX, and BLX. No BLX with immediate.
If branch taken, pipeline reloads (two cycles are added).
Load-store Single 16
2
b
(+P
a
if PC is destination)
LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, and
STRH, and T variants.
Load-store
Multiple
16
1+N
b
(+P
a
if PC loaded)
LDMIA, POP, PUSH, and STMIA.
Exception
generating
16 - BKPT stops in debug if debug enabled, fault if debug
disabled.
SVC faults to SVCall handler, see ARMv7-M architecture
specification for details.
Data operations
with immediate
32
1 (+P
a
if PC is destination)
ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S},
CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S},
MOV{S}, ORN{S}, and MVN{S}.
Data operations
with large
immediate
32 1 MOVW, MOVT, ADDW, and SUBW. MOVW and MOVT
have a 16-bit immediate (so can replace literal loads from
memory). ADDW and SUBW have a 12-bit immediate (so
also can replace many from memory literal loads).
Bit-field
operations
32 1 BFI, BFC, UBFX, and SBFX. These are bitwise operations
that enable control of position and size in bits. These both
support C/C++ bit fields (in structs) in addition to many
compare and some AND/OR assignment expressions.
Data operations
with 3 register
32
1 (+P
a
if PC is destination)
ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S},
CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S},
MOV{S}, ORN{S}, and MVN{S}. No PKxxx
instructions.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit