Instruction Timing
18-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Shift operations 32 1 ASR{S}, LSL{S}, LSR{S}, ROR{S}, and RRX{S}.
Miscellaneous 32 1 REV, REV16, REVSH, RBIT, CLZ, SXTB, SXTH,
UXTB, and UXTH. Extension instructions same as
corresponding ARM v6 16-bit instructions.
Table Branch 16
4+P
a
Table branches for switch/case use. These are LDR with
shifts and then branch.
Multiply 32 1 or 2 MUL, MLA, and MLS. MUL is one cycle and MLA and
MLS are two cycles.
Multiply with
64-bit result
32
3-7
c
UMULL, SMULL, UMLAL, and SMLAL. Cycle count
based on input sizes. That is, ABS(inputs) < 64K
terminates early.
Load-store
addressing
32 - Supports Format PC+/-imm12, Rbase+imm12,
Rbase+/-imm8, and adjusted register including shifts. T
variants used when in Privilege mode.
Load-store Single 32
2
b
(+P
a
if PC is destination)
LDR, LDRB, LDRSB, LDRH, LDRSH, STR, STRB, and
STRH, and T variants. PLD and PLI are both hints and so
act as a NOP.
Load-store
Multiple
32
1+N
b
(+P
a
if PC is loaded)
STM, LDM, LDRD, and STRD.
Load-store Special 32
1+N
b
LDREX, STREX, LDREXB, LDREXH, STREXB,
STREXH, CLREX. These fault if no local monitor (is IMP
DEF). LDREXD and STREXD are not included in this
profile.
Branches 32
1+P
a
B, BL, and B<cond>. No BLX (1) because it always
changes state. No BXJ.
System 32 1-2 MSR(2) and MRS(2) replace MSR/MRS but also do more.
These access the other stacks and also the status registers.
CPSIE/CPSID 32-bit forms are not supported.
No RFE or SRS.
System 16 1-2 CPSIE and CPSID are quick versions of MSR(2)
instructions and use the standard Thumb encodings, but
only permit use of i and f and not a.
Extended32 32 1 NOP and YIELD (hinted NOP). No MRS (1), MSR (1), or
SUBS (PC return link).
Table 18-1 Instruction timings (continued)
Instruction type Size Cycles count Description
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