ARM Cortex-M3 User Manual

Trace Port Interface Unit
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-17
Table 17-12 lists the bit assignments of the Integration Mode Control Register
Integration Register: TRIGGER
The register address, access type, and Reset state are:
Address
0xE0040EE8
Access Read only
Reset state
0x0
Figure 17-11 shows the bit assignments of the Integration Register : TRIGGER.
Figure 17-11 Integration Register : TRIGGER bit assignments
Table 17-13 lists the bit assignments of the Integration Register : TRIGGER bit
assignments.
Integration Register : FIFO data 0
The register address, access type, and Reset state are:
Address
0xE0040EEC
Access Read only
Table 17-12 Integration Mode Control Register bit assignments
Bits Field Function
[31:2] - Reserved, SBZ
[1] FIFO test mode Enables FIFO test mode
[0] Integration test mode Enables integration test mode
Reserved
31 0
1
TRIGGER input value
Table 17-13 Integration Register : TRIGGER bit assignments
Bits Field Function
[31:1] - Reserved
[0] TRIGGER input value Enables the TRIGGER input

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit