ARM Cortex-M3 User Manual

Embedded Trace Macrocell Interface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-9
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Figure 15-2 Conditional branch backwards taken
Figure 15-3 and Figure 15-4 show a conditional branch forwards not taken and taken.
The branch occurs speculatively in the decode phase of the opcode. The branch target
is a halfword aligned 16-bit opcode.
Figure 15-3 Conditional branch forwards not taken
Figure 15-4 Conditional branch forwards taken
0x1002
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT
HTRANSI
HADDRI
HCLK
0x1000
0001 0000
NONSEQ
0x0FF2
NONSEQ NONSEQ IDLE IDLE NONSEQ
0x0FF4 0x0FF8 0x0FFC 0x0FF0
1000
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT
HTRANSI
HADDRI
HCLK
0x1000 0x1002
0010 0000
NONSEQ
Fetch ahead of 0x1004+
0x1020
0000
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT
HTRANSI
HADDRI
HCLK
0x1000
0010 0000
NONSEQ
0x1002 0x1022
NONSEQ NONSEQ IDLE IDLE IDLE
0x1024 0x10280x1020
1000

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit