ARM Cortex-M3 User Manual

AC Characteristics
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 19-3
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Table 19-3 shows the timing parameters for the interrupt input ports.
Table 19-4 shows the timing parameters for the Advanced High-performance Bus
(AHB) ports.
Table 19-3 Interrupt input ports timing parameters
Input delay Min. Input delay Max. Signal name
Clock uncertainty 50% INTISR[239:0]
Clock uncertainty 50% INTNMI
Clock uncertainty 20% VECTADDR[9:0]
Clock uncertainty 20% VECTADDREN
Table 19-4 AHB input ports timing parameters
Input delay Min. Input delay Max. Signal name
Clock uncertainty 10% DNOTITRANS
Clock uncertainty 50% HRDATAI[31:0]
Clock uncertainty 50% HREADYI
Clock uncertainty 50% HRESPI[1:0]
Clock uncertainty 50% HRDATAD[31:0]
Clock uncertainty 50% HREADYD
Clock uncertainty 50% HRESPD[1:0]
Clock uncertainty 50% EXRESPD
Clock uncertainty 50% HRDATAS[31:0]
Clock uncertainty 50% HREADYS
Clock uncertainty 50% HRESPS[1:0]
Clock uncertainty 50% EXRESPS

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit