ARM Cortex-M3 User Manual

Core Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-3
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10.2 Core debug registers
The registers that provide debug operations are:
• Debug Halting Control and Status Register
• Debug Exception and Monitor Control Register on page 10-8.
• Debug Core Register Data Register on page 10-8
• Debug Exception and Monitor Control Register on page 10-8.
10.2.1 Debug Halting Control and Status Register
The purpose of the Debug Halting Control and Status Register (DHCSR) is to:
• provide status information about the state of the processor
• enable core debug
• halt and step the processor.
The DHCSR:
• is a 32-bit read/write register
• address is
0xE000EDF0 .
Note
The DHCSR is only reset from a system reset, including power on. Bit 16 of DHCSR
is Unpredictable on reset.
Figure 10-1 on page 10-4 shows the bit assignments in the register.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit