System Debug
11-42 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
AHB-AP Transfer Address Register
Use this register to program the address of the current transfer.
Table 11-30 describes the bit assignments of the AHB-AP Transfer Address Register.
[5:4] AddrInc Auto address increment and pack mode on Read or Write data access. Only increments if the
current transaction completes with no error.
Auto address incrementing and packed transfers are not performed on access to Banked Data
registers
0x10 - 0x1C
. The status of these bits is ignored in these cases.
Increments and wraps within a 4-KB address boundary, for example for word incrementing
from
0x1000 to 0x1FFC
. If the start is at
0x14A0
, then the counter increments to
0x1FFC
, wraps to
0x1000
, then continues incrementing to
0x149C
.
0b00 = auto increment off.
0b01 = increment single. Single transfer from corresponding byte lane.
0b10 = increment packed.
0b11 = reserved. No transfer.
Size of address increment is defined by the Size field [2:0].
Reset value: 0b00.
[3] - Reserved.
[2:0] SIZE Size of access field:
b000 = 8 bits
b001 = 16 bits
b010 = 32 bits
b011-111 are reserved.
Reset value: b000.
a. When clear, this bit prevents the debugger from setting the C_DEBUGEN bit in the Debug Halting Control and Status Register,
and so prevent the debugger from being able to halt the core.
Table 11-29 AHB-AP Control and Status Word Register bit assignments (continued)
Bits Field Function
Table 11-30 AHB-AP Transfer Address Register bit assignments
Bits Field Function
[31:0] ADDRESS Current transfer address.
No reset value.
To Next Page
Loading...
Need help?
General
