ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-23
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The register address, access type, and Reset state are:
Address
0xE000ED0C
Access Read/write
Reset state
0x00000000
Figure 8-11 shows the bit assignments of the Application Interrupt and Reset Control
Register.
Figure 8-11 Application Interrupt and Reset Control Register bit assignments
Table 8-17 describes the bit assignments of the Application Interrupt and Reset Control
Register.
31 16 15 0
VECTKEY/VECTKEYSTAT
12
Reserved
14
PRIGROUP
Reserved
11 810 7
ENDIANESS
VECTCLRACTIVE
VECTRESET
3
SYSRESETREQ
Table 8-17 Application Interrupt and Reset Control Register bit assignments
Bits Field Function
[31:16] VECTKEY Register key. Writing to this register requires
0x5FA in the VECTKEY field. Otherwise
the write value is ignored.
[31:16] VECTKEYSTAT Reads as
0xFA05 .
[15] ENDIANESS Data endianness bit:
1 = big endian
0 = little endian.
ENDIANESS is sampled from the BIGEND input port during reset. You cannot change
ENDIANESS outside of reset.
[14:11] - Reserved
[10:8] PRIGROUP Interrupt priority grouping field:

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit