ARM Cortex-M3 User Manual

Programmer’s Model
2-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Figure 2-5 Little-endian and big-endian memory formats
Halfword 0 at address E Halfword 1 at address C
Halfword 0 at address A Halfword 1 at address 8
Halfword 0 at address 6 Halfword 1 at address 4
Halfword 0 at address 2 Halfword 1 at address 0
Big-endian data format
31 24 23 16 15 8 7 0
Word at address 0
Byte 3 at
address 0
Byte 2 at
address 1
Byte 1 at
address 2
Byte 0 at
address 3
Word at address 4
Byte 3 at
address 4
Byte 2 at
address 5
Byte 1 at
address 6
Byte 0 at
address 7
Word at address 8
Byte 3 at
address 8
Byte 2 at
address 9
Byte 1 at
address A
Byte 0 at
address B
Word at address C
Byte 3 at
address C
Byte 2 at
address D
Byte 1 at
address E
Byte 0 at
address F
Halfword 1 at address E Halfword 0 at address C
Halfword 1 at address A Halfword 0 at address 8
Halfword 1 at address 6 Halfword 0 at address 4
Halfword 1 at address 2 Halfword 0 at address 0
Little-endian data format
31 24 23 16 15 8 7 0
Word at address 0
Byte 0 at
address 0
Byte 1 at
address 1
Byte 2 at
address 2
Byte 3 at
address 3
Word at address 4
Byte 0 at
address 4
Byte 1 at
address 5
Byte 2 at
address 6
Byte 3 at
address 7
Word at address 8
Byte 0 at
address 8
Byte 1 at
address 9
Byte 2 at
address A
Byte 3 at
address B
Word at address C
Byte 0 at
address C
Byte 1 at
address D
Byte 2 at
address E
Byte 3 at
address F

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit