ARM Cortex-M3 User Manual

Embedded Trace Macrocell
14-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 14-5 Clocks and resets
Name Description Direction
FCLK Clock for ETM logic which must be connected to the same FCLK as Cortex-M3. Input
PORRESETn Power on reset for the HCLK domain. Must not be the same as core HCLK reset
(SYSRESETn).
Input
Table 14-6 APB interface signals
Name Description Direction Clock domain
PSEL APB device select Input FCLK
PENABLE APB control signal Input FCLK
PADDR[11:2] APB Address Bus Input FCLK
PWRITE APB Transfer direction (!Read/Write) Input FCLK
PWDATA[31:0] APB Write Data Bus Input FCLK
PRDATA[31:0] APB Read Data Bus Output FCLK

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit