ARM Cortex-M3 User Manual

Signal Descriptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-11
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A.9 Private Peripheral Bus interface
Table A-9 lists the signals of the PPB interface.
Table A-9 Private Peripheral Bus interface
Name Direction Description
PADDR[19:2] Output 17-bit address. Only the bits that are relevant to the External Private Peripheral Bus are
driven.
PADDR31 Output This signal is driven HIGH when the AHB-AP is the requesting master. It is driven
LOW when DCore is the requesting master.
PSEL Output Indicates that a data transfer is requested.
PENABLE Output Strobe to time all accesses. Indicates the second cycle of an APB transfer.
PWDATA[31:0] Output 32-bit write data bus.
PWRITE Output Write not read.
PRDATA[31:0] Input Read data bus.
PREADY Input APB slave ready.
PSLVERR Input APB slave error.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit