ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-39
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11.7 AHB-AP
AHB-AP is an optional debug access port into the Cortex-M3 system, and provides
access to all memory and registers in the system, including processor registers through
the NVIC. System access is independent of the processor status. Either SW-DP or
SWJ-DP accesses AHB-AP.
AHB-AP is a master into the Bus Matrix. Transactions are made using the AHB-AP
programmer’s model, which generates AHB-Lite transactions into the Bus Matrix. See
Summary and description of the AHB-AP registers.
11.7.1 AHB-AP transaction types
AHB-AP does not do back-to-back transactions on the bus, and so all transactions are
non-sequential. AHB-AP can perform unaligned and bit-band transactions. The Bus
Matrix handles these. AHB-AP transactions are not subject to MPU lookups. AHB-AP
transactions bypass the FPB, and so the FPB cannot remap AHB-AP transactions.
SWJ/SW-DP initiated transaction aborts drive an AHB-AP supported sideband signal
called HABORT. This signal is driven into the Bus Matrix, which resets the Bus Matrix
state, so that AHB-AP can access the Private Peripheral Bus for last ditch debugging
such as read/stop/reset the core.
AHB-AP transactions are little endian.
11.7.2 Summary and description of the AHB-AP registers
Table 11-28 lists the AHB-AP registers.
Note
You can configure any of the AHB-AP registers to be present or not present. Any
register that is configured as not present reads as zero.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit