ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-33
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Figure 8-17 shows the bit assignments of the Memory Manage Fault Status Register.
Figure 8-17 Memory Manage Fault Status Register bit assignments
Table 8-22 describes the bit assignments of the Memory Manage Fault Status Register.
76543210
MMARVALID
MSTKERR
MUNSTKERR
DACCVIOL
IACCVIOL
Reserved
Reserved
Table 8-22 Memory Manage Fault Status Register bit assignments
Bits Field Function
[7] MMARVALID Memory Manage Address Register (MMAR) address valid flag:
1 = valid fault address in MMAR. A later-arriving fault, such as a bus fault, can clear a memory
manage fault.
0 = no valid fault address in MMAR.
If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard
Fault handler must clear this bit. This prevents problems on return to a stacked active
MemManage handler whose MMAR value has been overwritten.
[6:5] - Reserved.
[4] MSTKERR Stacking from exception has caused one or more access violations. The SP is still adjusted and
the values in the context area on the stack might be incorrect. The MMAR is not written.
[3] MUNSTKERR Unstack from exception return has caused one or more access violations. This is chained to the
handler, so that the original return stack is still present. SP is not adjusted from failing return
and new save is not performed. The MMAR is not written.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit