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Memory Protection Unit

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Table 9-3 describes the bit assignments of the MPU Control Register.

MPU Region Number Register

Use the MPU Region Number Register to select which protection region is accessed.

Then write to the MPU Region Base Address Register or the MPU Attributes and Size

The register address, access type, and Reset state are:

Address

0xE000ED98

Access Read/write

Reset state Unpredictable

Figure 9-3 on page 9-7 shows the bit assignments of the MPU Region Number Register.

Table 9-3 MPU Control Register bit assignments

Bits Field Function

[31:2] - Reserved.

[2] PRIVDEFENA This bit enables the default memory map for privileged access, as a background region, when

the MPU is enabled. The background region acts as if it was region number 1 before any

settable regions. Any region that is set up overlays this default map, and overrides it.

If this bit = 0, the default memory map is disabled, and memory not covered by a region faults.

When the MPU is enabled and PRIVDEFENA is enabled, the default memory map is as

described in Chapter 4 Memory Map. This applies to memory type, Execute Never (XN),

cache and shareable rules. However, this only applies to privileged mode (fetch and data

access). User mode code faults unless a region has been set up for its code and data.

When the MPU is disabled, the default map acts on both privileged and user mode code.

XN and SO rules always apply to the System partition whether this enable is set or not.

If the MPU is disabled, this bit is ignored.

Reset clears the PRIVDEFENA bit.

[1] HFNMIENA This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If

this bit = 1 and the ENABLE bit = 1, the MPU is enabled when in these handlers. If this bit =

0, the MPU is disabled when in these handlers, regardless of the value of ENABLE. If this bit

=1 and ENABLE = 0, behavior is Unpredictable.

Reset clears the HFNMIENA bit.

[0] ENABLE MPU enable bit:

1 = enable MPU

0 = disable MPU.

Reset clears the ENABLE bit.

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit