ARM Cortex-M3 User Manual

System Debug
11-28 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Table 11-18 describes the function settings of the DWT Function Registers.
Note
• If the ETM is not fitted, then ETM trigger is not possible.
Table 11-18 Settings for DWT Function Registers
Value Function
b0000 Disabled
b0001 EMITRANGE = 0, sample and emit PC through ITM
EMITRANGE = 1, emit address offset through ITM
b0010 EMITRANGE = 0, emit data through ITM on read and write.
EMITRANGE = 1, emit data and address offset through ITM on read or write.
b0011 EMITRANGE = 0, sample PC and data value through ITM on read or write.
EMITRANGE = 1, emit address offset and data value through ITM on read or write.
b0100 Watchpoint on PC match.
b0101 Watchpoint on read.
b0110 Watchpoint on write.
b0111 Watchpoint on read or write.
b1000 ETM trigger on PC match
b1001 ETM trigger on read
b1010 ETM trigger on write
b1011 ETM trigger on read or write
b1100 EMITRANGE = 0, sample data for read transfers
EMITRANGE = 1, sample Daddr [15:0] for read transfers
b1101 EMITRANGE = 0, sample data for write transfers
EMITRANGE = 1, sample Daddr [15:0] for write transfers
b1110 EMITRANGE = 0, sample PC + data for read transfers
EMITRANGE = 1, sample Daddr [15:0] + data for read transfers
b1111 EMITRANGE = 0, sample PC + data for write transfers
EMITRANGE = 1, sample Daddr [15:0] + data for write transfers

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit