ARM Cortex-M3 User Manual

System Control
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3.1.3 System debug registers
This section lists the system debug registers.
Flash Patch and Breakpoint registers
Table 3-3 gives a summary of the Flash Patch and Breakpoint (FPB) registers. For a
detailed description of the FPB registers, see Chapter 11 System Debug.
a. Bits [5], [3], [2], [1], [0] are reset by PORESETn. Bit [1] is also reset by SYSRESETn and by
writing a 1 to the VECTRESET bit of the Application Interrupt and Reset Control Register.
b. Bits [16], [17], [18], [19] are also reset by SYSRESETn and by writing a 1 to the VECTRESET
bit of the Application Interrupt and Reset Control Register.
Table 3-3 Flash patch register summary
Name Type Address Reset value Description
FP_CTRL Read/write
0xE0002000 Bit [0] is reset to 1'b0 Flash Patch Control Register
FP_REMAP Read/write
0xE0002004 - Flash Patch Remap Register
FP_COMP0 Read/write
0xE0002008 Bit [0] is reset to 1'b0 Flash Patch Comparator Registers
FP_COMP1 Read/write
0xE000200C Bit [0] is reset to 1'b0 Flash Patch Comparator Registers
FP_COMP2 Read/write
0xE0002010 Bit [0] is reset to 1'b0 Flash Patch Comparator Registers
FP_COMP3 Read/write
0xE0002014 Bit [0] is reset to 1'b0 Flash Patch Comparator Registers
FP_COMP4 Read/write
0xE0002018 Bit [0] is reset to 1'b0 Flash Patch Comparator Registers
FP_COMP5 Read/write
0xE000201C Bit [0] is reset to 1'b0 Flash Patch Comparator Registers
FP_COMP6 Read/write
0xE0002020 Bit [0] is reset to 1'b0 Flash Patch Comparator Registers
FP_COMP7 Read/write
0xE0002024 Bit [0] is reset to 1'b0 Flash Patch Comparator Registers
PID4 Read-only
0xE0002FD0 -
Value 0x04
PID5 Read-only 0xE0002FD4 -
Value 0x00
PID6 Read-only 0xE0002FD8 -
Value 0x00
PID7 Read-only 0xE0002FDC -
Value 0x00
PID0 Read-only 0xE0002FE0 -
Value 0x03
PID1 Read-only 0xE0002FE4 -
Value 0xB0

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit