ARM Cortex-M3 User Manual

Exceptions
5-32 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
5.13 Activation levels
When no exceptions are active, the processor is in Thread mode. When an ISR or fault
handler is active, the processor enters Handler mode. Table 5-13 lists the privilege and
stacks of the activation levels.
Table 5-14 summarizes the transition rules for all exception types and how they relate
to the access rules and stack model.
Table 5-13 Privilege and stack of different activation levels
Active exception Activation level Privilege Stack
None Thread mode Privileged or user Main or process
ISR active Asynchronous pre-emption level Privileged Main
Fault handler active Synchronous pre-emption level Privileged Main
Reset Thread mode Privileged Main
Table 5-14 Exception transitions
Active Exception Triggering event Transition type Privilege Stack
Reset Reset signal Thread
Privileged
or user
Main or
process
ISR
a
or NMI
b
Set-pending software instruction or
hardware signal
Asynchronous
pre-emption
Privileged Main
Fault:
Synchronous
pre-emption
Privileged Main
Hard fault
Bus fault
No CP
c
fault
Undefined instruction fault
Escalation
Memory access error
Absent CP access
Undefined instruction
Debug monitor Debug event when halting not enabled Synchronous Privileged Main
SVC
d
SVC instruction
External interrupt
a. Interrupt service routine.
b. Nonmaskable interrupt.
c. Coprocessor.
d. Software interrupt.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit