ARM Cortex-M3 User Manual

System Control
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3.1.6 Trace Port Interface Unit registers
Table 3-9 gives a summary of the Trace Port Interface Unit (TPIU) registers. For a
detailed description of the TPIU registers, see Chapter 17 Trace Port Interface Unit.
Table 3-9 TPIU registers
Name of register Type Address Reset value
Supported Sync Port Sizes Register Read-only
0xE0040000 0bxx0x
Current Sync Port Size Register Read/write
0xE0040004 0x01
Async Clock Prescaler Register Read/write 0xE0040010 0x0000
Selected Pin Protocol Register Read/write 0xE00400F0 0x01
Formatter and Flush Status Register Read-only 0xE0040300 0x08
Formatter and Flush Control Register Read/write 0xE0040304 0x00 or 0x102
Formatter Synchronization Counter Register Read-only 0xE0040308 0x00
Integration Register: ITATBCTR2 Read-only 0xE0040EF0 0x0
Integration Register: ITATBCTR0 Read-only 0xE0040EF8 0x0
Integration Mode Control Register Read/write 0xE0040F00 0x0
Integration register : FIFO data 0 Read only 0xE0040EEC 0x--000000
Integration register : FIFO data 1 Read only 0xE0040E
FC
0x--000000
Claim tag set register Read/write 0xE0040FA0 0xF
Claim tag clear register Read/write 0xE0040FA4 0x0
Device ID register Read only 0xE0040FCC 0x11
PID4 Read only 0xE0040FD0 0x04
PID5 Read only 0xE0040FD4 0x00
PID6 Read only 0xE0040FD8 0x00
PID7 Read only 0xE0040FDC 0x00
PID0 Read only 0xE0040FE0 0x23
PID1 Read only 0xE0040FE4 0xB9
PID2 Read only 0xE0040FE8 0x2B

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit