ARM Cortex-M3 User Manual

ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. B-1
Unrestricted Access Non-Confidential
Appendix B
Revisions
This appendix describes the technical changes between released issues of this book.
Table B-1 lists the differences between issue E and issue F, and Table B-2 on page B-5
lists the differences between issue F and issue G.
Table B-1 Differences between issue E and issue F
Change Location
Introductory processor information updated About the processor on page 1-2
Processor block diagram updated Figure 1-1 on page 1-5
Introductory information added, including:
• TPIU subsection
• Addition of note to SW/SWJ-DP subsection
• ROM table subsection.
Introductory processor core information updated Processor core on page 1-5
APB bus now version 3.0 Bus matrix on page 1-7

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit