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ARM Cortex-M3 User Manual

ARM Cortex-M3
410 pages
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Revisions
B-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Configurable options information expanded to include:
Added DWT configurability information
New subsections for ITM, AHB-AP, FPB and
Observation
New subsection added to list changes in functionality
between r1p1 and r2p0
Differences in functionality between r1p1 and r2p0 on
page 1-20
Information about the programmer’s model updated About the programmer’s model on page 2-2
Definition of ICI field of Execution Program Status Register
updated
Table 2-3 on page 2-8
Table of nonsupported Thumb instructions removed.
Second footnote on Table 5-1 removed. Table 5-1 on page 5-4
Addition of note to vector table and reset description Vector Table and Reset on page 5-20
Description of SLEEPING and SLEEPDEEP signals
updated.
System power management on page 7-3
Description of extending sleep functionality added Extending sleep on page 7-5
Addition of Auxiliary Control Register Table 8-1 on page 8-3 and NVIC register descriptions on
page 8-7
Irq 0 to 31 Priority Register amended to Irq 0 to 3 Priority
Register
Table 8-1 on page 8-3
Irq 236 to 239 Priority Register amended to Irq 224 to 239
Priority Register
Table 8-1 on page 8-3
HCLK changed to FCLK Level versus pulse interrupts on page 8-43
Addition of ascending MPU region priority information About the MPU on page 9-2
Extra paragraph added. About core debug on page 10-2
Debug Core Register Selector Register REGSEL bit field
function updated
Table 10-3 on page 10-7
Extra paragraph added. About system debug on page 11-2
Paragraph added about removing FPB FPB on page 11-6
Table B-1 Differences between issue E and issue F (continued)
Change Location

Table of Contents

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ARM Cortex-M3 Specifications

General IconGeneral
ArchitectureARMv7-M
Instruction SetThumb-2
Pipeline Stages3-stage
InterruptsNested Vectored Interrupt Controller (NVIC)
Interrupt ControllerNested Vectored Interrupt Controller (NVIC)
Memory Protection UnitOptional
Power ConsumptionVaries by implementation
Max Clock SpeedUp to 100 MHz
DebuggingJTAG and Serial Wire Debug (SWD)
Operating Voltage1.8V to 3.6V
Manufacturing ProcessVaries by implementation
Core Type32-bit

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