EasyManuals Logo

ARM Cortex-M3 User Manual

ARM Cortex-M3
410 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #340 background imageLoading...
Page #340 background image
Trace Port Interface Unit
17-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
17.2 TPIU registers
This section describes the TPIU registers. It contains the following:
Summary of the TPIU registers
Description of the TPIU registers on page 17-9.
17.2.1 Summary of the TPIU registers
Table 17-5 provides a summary of the TPIU registers.
Note
You can configure any of the TPIU registers to be present or not present. Any register
that is configured as not present reads as zero.
Table 17-5 TPIU registers
Name of register Type Address Reset value Page
Supported Sync Port Sizes Register Read-only
0xE0040000
0bxx0x page 17-9
Current Sync Port Size Register Read/write
0xE0040004 0x01
page 17-10
Async Clock Prescaler Register Read/write
0xE0040010 0x0000
page 17-10
Selected Pin Protocol Register Read/write
0xE00400F0 0x01
page 17-11
Formatter and Flush Status Register Read-only
0xE0040300 0x08
page 17-11
Formatter and Flush Control Register Read/write
0xE0040304 0x102
page 17-12
Formatter Synchronization Counter Register Read-only
0xE0040308 0x00
page 17-14
Integration Register: TRIGGER Read-only
0xE0040EE8 0x0
page 17-17
Integration Register: ITATBCTR2 Read-only
0xE0040EF0 0x0
page 17-15
Integration Register: ITATBCTR0 Read-only
0xE0040EF8 0x0
page 17-15
Integration Mode Control Register Read/write
0xE0040F00 0x0
page 17-16
Integration register : FIFO data 0 Read only
0xE0040EEC 0x--000000
page 17-17
Integration register : FIFO data 1 Read only
0xE0040EFC 0x--000000
page 17-18
Claim tag set register Read/write
0xE0040FA0 0xF
page 17-20
Claim tag clear register Read/write
0xE0040FA4 0x0
page 17-19

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ARM Cortex-M3 and is the answer not in the manual?

ARM Cortex-M3 Specifications

General IconGeneral
ArchitectureARMv7-M
Instruction SetThumb-2
Pipeline Stages3-stage
InterruptsNested Vectored Interrupt Controller (NVIC)
Interrupt ControllerNested Vectored Interrupt Controller (NVIC)
Memory Protection UnitOptional
Power ConsumptionVaries by implementation
Max Clock SpeedUp to 100 MHz
DebuggingJTAG and Serial Wire Debug (SWD)
Operating Voltage1.8V to 3.6V
Manufacturing ProcessVaries by implementation
Core Type32-bit

Related product manuals