ARM Cortex-M3 User Manual

Trace Port Interface Unit
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-15
Integration Test Registers
Use the Integration Test Registers to perform topology detection of the TPIU with other
devices in a Cortex-M3 system. These registers enable direct control of outputs and the
ability to read the value of inputs. The processor provides two Integration Test
Registers:
• Integration Test Register - ITATBCTR2
• Integration Test Register - ITATBCTR0.
Integration Test Register-ITATBCTR2
The register address, access type, and Reset state are:
Address
0xE0040EF0
Access Read only
Reset state
0x0
Figure 17-8 shows the bit assignments of the Integration Test Register bit assignments.
Figure 17-8 Integration Test Register-ITATBCTR2 bit assignments
Table 17-10 describes the bit assignments of the Integration Test Register bit
assignments.
Integration Test Register-ITATBCTR0
The register address, access type, and Reset state are:
Address
0xE0040EF8
Access Read only
Reset state
0x0
31
0
Reserved
1
ATREADY1
ATREADY2
Table 17-10 Integration Test Register-ITATBCTR2 bit assignments
Bits Field Function
[31:1] - Reserved.
[0] ATREADY1, ATREADY2 This bit reads or sets the value of ATREADYS1 and ATREADYS2.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit