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Embedded Trace Macrocell Interface

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Figure 15-9 Example of an opcode sequence

FCLK

ETMLSU

ETMIVALID

ETMIBRANCH

ETMIINDBR

ETMIA

ETMFOLD

BRCHSTAT

ETMICCFAIL

HADDRI

HTRANSI

DEn

Decode op

Execute op

0x811 0x814 0x823 0x826

Idle NONSEQ

0010 1000 0000 0000 0100 0000 0000 0010 0101

NONSEQ

Idle

NONSEQ

0000

0x102c

0x1030

0x1040

0x1044

0x1048

0x104C

0x1050

0x1054

ADD CMP BEQ CMPLDR LDR ADD NOP BX

ITE/LDR

BEQ BXCMP

LDR ADD CMP BEQADD LDRLDR ADD NOP BXCMP BEQ BXCMP

0000

0x810 0x812

0x813

0x820

0x822

0x824

0x825

0x7E2

0x7E3

0x7E4

0xFC4

0xFC8

0xFCC

0xFC8

0xFD0

NONSEQ

0x12AC

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit