ARM Cortex-M3 User Manual

Signal Descriptions
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A.13 AHB Trace Macrocell interface
Table A-13 lists the signals of the AHB Trace Macrocell (HTM) interface
Table A-13 HTM interface
Name Direction Description
HTMDHADDR[31:0] Output 32-bit address
HTMDHTRANS[1:0] Output Output indicates the type of the current data transfer. Can be IDLE,
NONSEQUENTIAL, OR SEQUENTIAL.
HTMDHSIZE[1:0] Output Indicates the size of the access. Can be 8, 16, or 32 bits.
HTMDHBURST[2:0] Output Output indicates if the transfer is part of a burst.
HTMDHPROT[3:0] Output Provides information on the access.
HTMDHWDATA[31:0] Output 32-bit write data bus.
HTMDHWRITE Output Write not read.
HTMDHRDATA[31:0] Output Read data bus.
HTMDHREADY Output Ready signal.
HTMDHRESP[1:0] Output The transfer response status. OKAY or ERROR.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit