ARM Cortex-M3 User Manual

Embedded Trace Macrocell Interface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-7
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The ALU register based branches and LSU PC modifying instructions are recognized
as conditional branches, b0011, if they are present in IT blocks. Otherwise they are
recognized as unconditional branches, b0101.
Table 15-3 Branches and stages evaluated by the processor
Branch Instruction Instruction size Stage branch target is issued Notes
B <imm> 16 bits Decode -
B <imm> 32 bits Decode -
BL 32 bits Decode If LR is not being written during
decode.
BLX LR 16 bits Decode If LR is not being written during
decode.
BX LR 16 bits Decode If LR is not being written during
decode.
MOV PC, LR 16 bits Decode If LR is not being written during
decode.
ADD PC 32 bits Execute -
BLX 16 bits Execute If LR is not the source register or
if LR is being written during
decode.
BX 16 bits Execute If LR is not the source register or
if LR is being written during
decode.
CBZ, CBNZ 16 bits Execute -
ISB 16 bits Execute -
LDR PC 32 bits Execute -
LDM to PC 32 bits Execute -
MOV PC 32 bits Execute If LR is not the source register or
if LR is being written during
decode and LR is the source
register.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit