ARM Cortex-M3

Clocking and Resets
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 6-5
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6.3 Cortex-M3 reset modes
The reset signals present in the processor design enable you to reset different parts of
the design independently. Table 6-4 shows the reset signals, and the combinations and
possible applications that you can use them in.
Note
PORESETn resets a superset of the SYSRESETn logic.
6.3.1 Power-on reset
Figure 6-1 on page 6-6 shows the reset signals for the macrocell.
Table 6-4 Reset modes
Reset mode SYSRESETn nTRST PORESETn Application
Power-on reset x 0 0 Reset at power up, full system reset. Cold reset.
System reset 0 x 1 Reset of processor core and system components,
excluding debug.
SWJ-DP reset 1 0 1 Reset of SWJ-DP logic.