ARM Cortex-M3 User Manual

System Debug
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DWT Program Counter Sample Register
Use the DWT Program Counter Sample Register (PCSR) to enable coarse-grained
software profiling using a debug agent, without changing the currently executing code.
If the core is not in debug state, the value returned is the instruction address of a recently
executed instruction.
If the core is in debug state, the value returned is
0xFFFFFFFF .
The register address, access type, and Reset state are:
Address
0xE000101C
Access Read-only
Reset state Unpredictable
DWT Program Counter Sample Register bit assignments describes the field of the DWT
PCSR.
DWT Comparator Registers
Use the DWT Comparator Registers 0-3 to write the values that trigger watchpoint
events.
The register address, access type, and Reset state are:
Address
0xE0001020 , 0xE0001030 , 0xE0001040 , 0xE0001050
Access Read/write
Reset state -
Table 11-15 describes the field of DWT Comparator Registers 0-3.
Table 11-14 DWT Program Counter Sample Register bit assignments
Bits Field Function
[31:0] EIASAMPLE Execution instruction address sample, or
0xFFFFFFFF if the core is halted.
Table 11-15 DWT Comparator Registers 0-3 bit assignments
Field Name Definition
[31:0] COMP Data value to compare against PC and the data address as given by DWT_FUNCTIONx.
DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT).
DWT_COMP1 can also compare against data values so that data matching can be performed
(DATAVMATCH).

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit