ARM Cortex-M3 User Manual

Trace Port Interface Unit
17-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Figure 17-6 shows the bit assignments of the Formatter and Flush Status Register.
Figure 17-6 Formatter and Flush Status Register bit assignments
Table 17-8 describes the bit assignments of the Formatter and Flush Status Register.
Formatter and Flush Control Register
The Formatter and Flush Control Register.
The register address, access type, and Reset state are:
Address
0xE0040304
Access Read/write
Reset state
0x102
Figure 17-7 on page 17-13 shows the bit assignments of the Formatter and Flush
Control Register.
31 2 0
Reserved
1
FlInProg
3
FtStopped
TCPresent
FtNonStop
4
Table 17-8 Formatter and Flush Status Register bit assignments
Bits Field Function
[31:4] - Reserved
[3] FtNonStop Formatter cannot be stopped
[2] TCPresent This bit always reads zero
[1] FtStopped This bit always reads zero
[0] FlInProg This bit always reads zero

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit