ARM Cortex-M3 User Manual

System Debug
11-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 11-5 Flash Patch Comparator Registers bit assignments
Bits Field Function
[31:30] REPLACE This selects what happens when the COMP address is matched.
It is interpreted as:
b00 = remap to remap address. See FP_REMAP
b01 = set BKPT on lower halfword, upper is unaffected
b10 = set BKPT on upper halfword, lower is unaffected
b11 = set BKPT on both lower and upper halfwords.
Settings other than b00 are only valid for instruction comparators. Literal comparators ignore
non-b00 settings.
Address remapping only takes place for the b00 setting.
[29] - Reserved
[28:2] COMP Comparison address.
[1] - Reserved.
[0] ENABLE Compare and remap enable for Flash Patch Comparator Register n:
1 = Flash Patch Comparator Register n compare and remap enabled
0 = Flash Patch Comparator Register n compare and remap disabled.
The ENABLE bit of FP_CTRL must also be set to enable comparisons.
Reset clears the ENABLE bit.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit