ARM Cortex-M3 User Manual

Debug Port
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13.1 About the DP
The processor contains an Advanced High-performance Bus Access Port (AHB-AP)
interface for debug accesses. An external DP component accesses this interface. The
Cortex-M3 system supports three possible DP implementations:
•The Serial Wire JTAG Debug Port (SWJ-DP). The SWJ-DP is a standard
CoreSight debug port that combines JTAG-DP and Serial Wire Debug Port
(SW-DP).
• The SW-DP. This provides a two-pin (clock + data) interface to the AHB-AP port.
• No DP present. If no debug functionality is present within the processor, a DP is
not required.
Note
The SWJ-DP is designed to permit pin sharing of JTAG-TDO and JTAG-TDI when
they are not being used for JTAG debug access. When used together with a Cortex-M3
TPIU, there are different options for the connection of Serial Wire Output (SWO), see
Serial wire output connection on page 17-21.
The two DP implementations provide different mechanisms for debug access to the
processor. Your implementation must contain only one of these components.
Note
Your implementation might contain an alternative implementor-specific DP instead of
SW-DP or SWJ-DP. See your implementor for details.
For more detailed information on the DP components, see the CoreSight Components
Technical Reference manual.
For more information on the AHB-AP, see AHB-AP on page 11-39.
The DP and AP together are referred to as the Debug Access Port (DAP).
For more detailed information on the debug interface, see the ARM Debug Interface v5,
Architecture Specification.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit