ARM Cortex-M3 User Manual

ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-1
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Chapter 14
Embedded Trace Macrocell
This chapter describes the Embedded Trace Macrocell (ETM). It contains the following
sections:
• About the ETM on page 14-2
• Data tracing on page 14-7
• ETM resources on page 14-8
• Trace output on page 14-11
• ETM architecture on page 14-12
• ETM programmer’s model on page 14-16.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit