ARM Cortex-M3 User Manual

System Control
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 3-7
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Data Watchpoint and Trace registers
Table 3-4 gives a summary of the Data Watchpoint and Trace (DWT) registers. For a
detailed description of the DWT registers, see Chapter 11 System Debug.
PID2 Read-only 0xE0002FE8 -
Value 0x2B
PID3 Read-only 0xE0002FEC -
Value 0x00
CID0 Read-only 0xE0002FF0 -
Value 0x0D
CID1 Read-only 0xE0002FF4 -
Value 0xE0
CID2 Read-only 0xE0002FF8 -
Value 0x05
CID3 Read-only 0xE0002FFC -
Value 0xB1
Table 3-3 Flash patch register summary (continued)
Name Type Address Reset value Description
Table 3-4 DWT register summary
Name Type Address
Reset
value
Description
DWT_CTRL Read/write
0xE0001000 0x40000000 DWT Control Register
DWT_CYCCNT Read/write
0xE0001004 0x00000000 DWT Current PC Sampler Cycle Count Register
DWT_CPICNT Read/write
0xE0001008 - DWT Current CPI Count Register
DWT_EXCCNT Read/write
0xE000100C - DWT Current Interrupt Overhead Count Register
DWT_SLEEPCNT Read/write
0xE0001010 - DWT Current Sleep Count Register
DWT_LSUCNT Read/write
0xE0001014 - DWT Current LSU Count Register
DWT_FOLDCNT Read/write
0xE0001018 - DWT Current Fold Count Register
DWT_PCSR Read-only
0xE000101C -DWT PC Sample Register
DWT_COMP0 Read/write
0xE0001020 - DWT Comparator Register
DWT_MASK0 Read/write
0xE0001024 - DWT Mask Registers
DWT_FUNCTION0 Read/write
0xE0001028 0x00000000 DWT Function Registers
DWT_COMP1 Read/write
0xE0001030 - DWT Comparator Register

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit