ARM Cortex-M3 User Manual

System Control
3-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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DWT_MASK1 Read/write 0xE0001034 - DWT Mask Registers
DWT_FUNCTION1 Read/write
0xE0001038 0x00000000 DWT Function Registers
DWT_COMP2 Read/write
0xE0001040 - DWT Comparator Register
DWT_MASK2 Read/write
0xE0001044 - DWT Mask Registers
DWT_FUNCTION2 Read/write
0xE0001048 0x00000000 DWT Function Registers
DWT_COMP3 Read/write
0xE0001050 - DWT Comparator Register
DWT_MASK3 Read/write
0xE0001054 - DWT Mask Registers
DWT_FUNCTION3 Read/write
0xE0001058 0x00000000 DWT Function Registers
PID4 Read-only
0xE0001FD0 0x04 Va lu e 0x04
PID5 Read-only 0xE0001FD4 0x00 Va lu e 0x00
PID6 Read-only 0xE0001FD8 0x00 Va lu e 0x00
PID7 Read-only 0xE0001FDC 0x00 Va lu e 0x00
PID0 Read-only 0xE0001FE0 0x02 Va lu e 0x02
PID1 Read-only 0xE0001FE4 0xB0 Va lu e 0xB0
PID2 Read-only 0xE0001FE8 0x0B0 Va lu e 0x2B
PID3 Read-only 0xE0001FEC 0x00 Va lu e 0x00
CID0 Read-only 0xE0001FF0 0x0D Va lu e 0x0D
CID1 Read-only 0xE0001FF4 0xE0 Va lu e 0xE0
CID2 Read-only 0xE0001FF8 0x05 Va lu e 0x05
CID3 Read-only 0xE0001FFC 0xB1 Va lu e 0xB1
Table 3-4 DWT register summary (continued)
Name Type Address
Reset
value
Description

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit