ARM Cortex-M3 User Manual

System Control
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 3-13
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3.1.7 Embedded Trace Macrocell registers
Table 3-10 gives a summary of the Embedded Trace Macrocell (ETM) registers. For a
detailed description of the ETM registers, see Chapter 14 Embedded Trace Macrocell.
PID3 Read only 0xE0040FEC 0x00
CID0 Read only 0xE0040FF0 0x0D
CID1 Read only 0xE0040FF4 0x90
CID2 Read only 0xE0040FF8 0x05
CID3 Read only 0xE0040FFC 0xB1
Table 3-9 TPIU registers (continued)
Name of register Type Address Reset value
Table 3-10 ETM registers
Name Type Address Present
ETM Control Read/write
0xE0041000 Yes
Configuration Code Read-only
0xE0041004 Yes
Trigger event Write-only
0xE0041008 Yes
ASIC Control Write-only
0xE004100C No
ETM Status Read-only or read/write
0xE0041010 Yes
System Configuration Read-only
0xE0041014 Yes
TraceEnable Write-only
0xE0041018 , 0xE004101C No
TraceEnable Event Write-only
0xE0041020 Yes
TraceEnable Control 1 Write-only
0xE0041024 Yes
FIFOFULL Region Write-only
0xE0041028 No
FIFOFULL Level Write-only or read/write
0xE004102C Yes
ViewData Write-only
0xE0041030-0xE004103C No
Address Comparators Write-only
0xE0041040- 0xE004113C No
Counters Write-only
0xE0041140-0xE004157C No

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit