ARM Cortex-M3 User Manual

System Control
3-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Sequencer Read/write 0xE0041180- 0xE0041194, 0xE0041198 No
External Outputs Write-only
0xE00411A0-0xE00411AC No
CID Comparators Write-only
0xE00411B0-0xE00411BC No
Implementation specific Write-only
0xE00411C0-0xE00411DC No
Synchronization Frequency Read-only
0xE00411E0 Yes
ETM ID Read-only
0xE00411E4 Yes
Configuration Code Extension Read-only
0xE00411E8 Yes
Extended External Input Selector Write-only
0xE00411EC No
TraceEnable Start/Stop Embedded ICE Read/write
0xE00411F0 Yes
Embedded ICE Behavior Control Write-only
0xE00411F4 No
CoreSight Trace ID Read/write
0xE0041200 Yes
OS Save/Restore Write-only
0xE0041304-0xE0041308 No
ITMISCIN Read-only
0xE0041EE0 Yes
ITTRIGOUT Write-only
0xE0041EE8 Yes
ITATBCTR2 Read-only
0xE0041EF0 Yes
ITATBCTR0 Write-only
0xE0041EF8 Yes
Integration Mode Control Read/write
0xE0041F00 Yes
Claim Tag Read/write
0xE0041FA0-0xE0041FA4 Yes
Lock Access Write-only
0xE0041FB0-0xE0041FB4 Yes
Authentication Status Read-only
0xE0041FB8 Yes
Device Type Read-only
0xE0040FCC Yes
Peripheral ID 4 Read-only
0xE0041FD0 Yes
Peripheral ID 5 Read-only
0xE0041FD4 Yes
Peripheral ID 6 Read-only
0xE0041FD8 Yes
Peripheral ID 7 Read-only
0xE0041FDC Yes
Table 3-10 ETM registers (continued)
Name Type Address Present

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit