ARM Cortex-M3 User Manual

Trace Port Interface Unit
17-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
17.1 About the TPIU
The TPIU is an optional component that acts as a bridge between the on-chip trace data
from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell
(ITM), with separate IDs, to a data stream, encapsulating IDs where required, that is
then captured by a Trace Port Analyzer (TPA).
The TPIU is specially designed for low-cost debug. It is a special version of the
CoreSight TPIU, and you can replace it with CoreSight components if system
requirements demand the additional features of the CoreSight TPIU.
There are two configurations of the TPIU:
• A configuration that supports ITM debug trace.
• A configuration that supports both ITM and ETM debug trace.
If the implementation requires no trace support then the TPIU might not be present.
Note
If your Cortex-M3 system uses the optional ETM component, you must use the TPIU
configuration that supports both ITM and ETM debug trace. For a full description of the
ETM, see Chapter 14 Embedded Trace Macrocell.
17.1.1 TPIU block diagrams
Figure 17-1 on page 17-3 and Figure 17-2 on page 17-4 show the component layout of
the TPIU for both configurations.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit