ARM Cortex-M3 User Manual

Core Debug
10-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Figure 10-1 Debug Halting Control and Status Register bit assignments
Table 10-2 shows the bit functions of the Debug ID Register.
Reserved
Reserved
DBGKEY
31 2103456789101112131415161718192021222324252627282930
RAZRAZ
Write
Read
C_SNAPSTALL
C_MASKINTS
C_STEP
C_HALT
C_DEBUGEN
S_RESET_ST
S_RETIRE_ST
S_LOCKUP
S_SLEEP
S_HALT
S_REGRDY
Reserved
Table 10-2 Debug Halting Control and Status Register
Bits Type Field Function
[31:16] Write DBGKEY Debug Key.
0xA05F must be written whenever this register is written. Reads
back as status bits [25:16]. If not written as Key, the write operation is
ignored and no bits are written into the register.
[31:26] - - Reserved, RAZ.
[25] Read S_RESET_ST Indicates that the core has been reset, or is now being reset, since the last
time this bit was read. This a sticky bit that clears on read. So, reading twice
and getting 1 then 0 means it was reset in the past. Reading twice and getting
1 both times means that it is being reset now (held in reset still).
[24] Read S_RETIRE_ST Indicates that an instruction has completed since last read. This is a sticky
bit that clears on read. This determines if the core is stalled on a load/store
or fetch.
[23:20] - - Reserved, RAZ.
[19] Read S_LOCKUP Reads as one if the core is running (not halted) and a lockup condition is
present.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit