ARM Cortex-M3 User Manual

Core Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-5
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[18] Read S_SLEEP Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must
use C_HALT to gain control or wait for interrupt to wake-up. For more
information on SLEEP-ON-EXIT see Table 7-1 on page 7-3.
[17] Read S_HALT The core is in debug state when S_HALT is set.
[16] Read S_REGRDY Register Read/Write on the Debug Core Register Selector register is
available. Last transfer is complete.
[15:6] - - Reserved.
[5] Read/write C_SNAPSTALL If the core is stalled on a load/store operation the stall ceases and the
instruction is forced to complete. This enables Halting debug to gain control
of the core. It can only be set if:
C_DEBUGEN = 1
C_HALT = 1.
The core reads S_RETIRE_ST as 0. This indicates that no instruction has
advanced. This prevents misuse.
The bus state is Unpredictable when this is used.
S_RETIRE can detect core stalls on load/store operations.
[4] - - Reserved.
[3] Read/write C_MASKINTS Mask interrupts when stepping or running in halted debug. Does not affect
NMI, which is not maskable. Must only be modified when the processor is
halted (S_HALT == 1). Also does not affect fault exceptions and SVC
caused by execution of the instructions. CMASKINTS must be set or
cleared before halt is released. This means that the writes to set or clear
C_MASKINTS and to set or clear C_HALT must be separate.
[2] Read/write C_STEP Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no
effect. Must only be modified when the processor is halted (S_HALT == 1).
[1] Read/write C_HALT Halts the core. This bit is set automatically when the core Halts. For
example Breakpoint. This bit clears on core reset. This bit can only be
written if C_DEBUGEN is 1, otherwise it is ignored. When setting this bit
to 1, C_DEBUGEN must also be written to 1 in the same value (value[1:0]
is 2’b11). The core can halt itself, but only if C_DEBUGEN is already 1
and only if it writes with b11).
[0] Read/write C_DEBUGEN Enables debug. This can only be written by AHB-AP and not by the core. It
is ignored when written by the core, which cannot set or clear it.
The core must write a 1 to it when writing C_HALT to halt itself.
Table 10-2 Debug Halting Control and Status Register (continued)
Bits Type Field Function

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit