Exceptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-17
Unrestricted Access Non-Confidential
5.8 Exit
The last instruction of an ISR loads the PC with value
0xFFFFFFFX
that was LR on
exception entry. This indicates to the processor that the ISR is complete, and the
processor initiates the exception exit sequence. See Returning the processor from an ISR
on page 5-18 for the instructions that you can use to return the processor from an ISR.
5.8.1 Exception exit
When returning from an exception, the processor is either:
• tail-chaining to a pending exception if the pending exception is of higher priority
than all stacked exceptions
• returning to the last stacked ISR if there are no pending exceptions or if the
highest priority stacked exception is of higher priority than the highest priority
pending exception
• returning to the Thread mode if there are no pending or stacked exceptions.
Table 5-5 describes the postamble sequence.
Figure 5-5 on page 5-18 shows an example of exception exit timing.
Table 5-5 Exception exit steps
Action Description
Pop eight registers Pops PC, xPSR, r0, r1, r2, r3, r12 and LR from stack selected by EXC_RETURN
and adjusts SP, if not pre-empted.
Load current active interrupt number
a
and reverse stack-alignment
adjustment
Loads current active interrupt number from bits [8:0] of stacked IPSR word. The
processor uses this to track which exception to return to and to clear the
activation bit on return. When bits [8:0] are zero, the processor returns to Thread
Mode.
Select SP If returning to an exception, SP is SP_main. If returning to Thread Mode, SP can
be SP_main or SP_process.
a. Because of dynamic priority changes, the NVIC uses interrupt numbers instead of interrupt priorities to determine which ISR
is current.
To Next Page
Loading...
Need help?
General
