ARM Cortex-M3 User Manual

Exceptions
5-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Figure 5-4 on page 5-15 shows the latest point at which INTISR[9] can pre-empt
before the first instruction of the ISR for INTISR[8] enters Fetch stage. The ISR fetch
for INTISR[8] is aborted when INTISR[9] is received, and the processor then initiates
the vector fetch for INTISR[9]. A higher priority interrupt after that point is managed
as pre-emption.
In the cycle that the ISR for INTISR[9] enters execute:
• ETMINSTAT[2:0] indicates that the ISR has been entered (3'b001). This is a
1-cycle pulse.
• CURRPRI[7:0] indicates the priority of the active interrupt. CURRPRI remains
asserted throughout the duration of the ISR.
• ETMINTNUM[8:0] indicates the number of the active interrupt.
ETMINTNUM remains asserted throughout the duration of the ISR.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit